UW Trains

UW Trains You can sleep when you're dead!

11/03/2011

We have shiny new trains! Sadly, they don't have the honking or sound effect auxiliary functions :(

10/27/2011

Watching someone else reset all the switches in succession in front of Cowan and describe it as a guilty pleasure may well have been the highlight of the day.

10/22/2011

Why is the trains lab empty on a Saturday afternoon? Everyone should be ashamed.

10/19/2011

The sound of the switches flipping in quick succession with fast interrupt-driven IO makes me weak at the knees

10/17/2011

Pro-tip: When caches make your code slower, it may be time to reconsider some design choices

10/12/2011

I haven't seen the lab this full since the night before A0. Interrupts are serious business, apparently.

10/07/2011

11 microseconds is the current record for completing a 64 byte send-receive-reply transaction. It involves Duff's device, -O2, caches on, fast processor clocks, hacking the bus clock mode, and a non-negligible dose of black-magic

10/06/2011

Ricing out memcpy, or doing the K2 write-up? I think we all know the answer to that question

10/05/2011

pro-tip #3: Interrupts being asserted and jumping to ISRs are two distinct things

09/25/2011

pro-tip #2: breaker #10 (TEC Unit)

09/24/2011

How long is your context switch? Historic record (known so far) is 13 instructions

In lieu of actual locks...
09/23/2011

In lieu of actual locks...

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